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ethernet/gigabit ethernet clock generator data sheet ad9574 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2014 analog devices, inc. all rights reserved. technical support www.analog.com features redundant input reference clock capability reference monitoring function fully integrated vco/pll core jitter (rms) 0.234 ps rms jitter (10 khz to 10 mhz) at 156.25 mhz 0.243 ps rms jitter (12 khz to 20 mhz) at 156.25 mhz input frequency: 19.44 mhz or 25 mhz preset frequency translations using a 19.44 mhz input reference 19.44 mhz, 38.88 mhz, 77.76 mhz, 155.52 mhz using a 25 mhz input reference 25 mhz, 33.33 mhz, 50 mhz, 66.67 mhz, 80 mhz, 100 mhz, 125 mhz, 133.3 mhz, 156.25 mhz, 160 mhz, 312.5 mhz output drive formats: hstl, lvds, hcsl, and 1.8 v and 3.3 v cmos integrated loop filter (requires a single external capacitor) 2 copies of reference clock output device configuration via strapping pins (pprx) space-saving 7 mm 7 mm 48-lead lfcsp 3.3 v operation applications ethernet line cards, switches, and routers sata and pci express low jitter, low phase noise clock generation functional block diagram figure 1. general description the ad9574 provides a multiple output clock generator function comprising a dedicated phase-locked loop (pll) core optimized for ethernet and gigabit ethernet line card applications. the integer-n pll design is based on the analog devices, inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. the ad9574 also benefits other applications requiring low phase noise and jitter performance. configuring the ad9574 for a particular application requires only the connection of external pull-up or pull-down resistors to the appropriate pin program reader pins (pprx). these pins provide control of the internal dividers for establishing the desired frequency translations, clock output functionality, and input reference functionality. connecting an external 19.44 mhz or 25 mhz oscillator to one or both of the ref0_p/ref0_n or ref1_p/ref1_n reference inputs results in a set of output frequencies prescribed by the pprx pins. connecting a stable clock source (8 khz/10 mhz/19.44 mhz/25 mhz/38.88 mhz) to the monitor clock input enables the optional monitor circuit providing quality of service (qos) status for ref0 or ref1. the pll section consists of a low noise phase frequency detector (pfd), a precision charge pump (cp), a partially integrated loop filter (lf), a low phase noise voltage controlled oscillator (vco), and feedback and output dividers. the divider values depend on the pprx pins. the integrated loop filter requires only a single external capacitor connected to the lf pin. the ad9574 is packaged in a 48-lead 7 mm 7 mm lfcsp, requiring only a single 3.3 v supply. the operating temperature range is ?40c to +85c. note that throughout this data sheet, out0 to out6, ref0, and ref1 refer to the respective channels, which consist of the differential pins, out0_p/out0_n to out6_p/out6_n, ref0_p/ref0_n, and ref1_p/ref1_n, respectively. 07501-001 rx rx reference switch refmon ref0_p ad9574 pfd/ cp lf lf vco ld ppr control pprx out1_p out0_p 1/2 1/2 dividers ref0_n ref1_p ref1_n out0_n out1_n ref_act ref_sw ref_flo ref_fhi mclk_x ref_sel out2_p out2_n out3_p out3_n out4_p out4_n out5_p out5_n out6_p out6_n reference monitor
ad9574 data sheet tab le of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 out0 channel absolute clock jitter ........................................ 3 out1 channel absolute clock jitter ........................................ 3 out2 a nd out3 channels absolute clock jitter ..................... 3 out4 and out5 channels absolute clock jitter ..................... 4 out6 channel absolute clock jitter ........................................ 5 clock outputs (out0_x to out6_x) static ........................ 6 clock outputs (out0_x to out6_x) dynamic .................. 6 monitor clock inputs (mclk_x) static ................................ 7 monitor clock inputs (mclk_x) dynamic .......................... 8 reference inputs (ref0_x and ref1_x) s tatic ..................... 8 reference inputs (ref0_x and ref1_x) dynamic .............. 8 reference switchover output disturbance .......................... 9 control pins .................................................................................. 9 status pins .................................................................................... 10 power supply and dissipation .................................................. 10 timing specifications ................................................................ 11 timing diagrams ........................................................................ 12 absolute maximum ratings .......................................................... 13 thermal resistance .................................................................... 13 esd caution ................................................................................ 13 pin configuration and function descriptions ........................... 14 typical performance characteristics ........................................... 17 terminology .................................................................................... 20 theory of operation ...................................................................... 21 overview ..................................................................................... 21 pprx pins .................................................................................... 21 ppr0 reference clock input configuration ................... 22 ppr1 frequency translation settings .............................. 22 ppr2 out0 and out1 configuration ........................... 23 ppr 3 o ut4 and out5 configuration ........................... 23 ppr4 out6 configuration ............................................... 24 ppr5 reference monitor threshold ................................. 24 ppr6 monitor clock (mclk_x) input configuration . 24 dependency of ppr3 and ppr4 on ppr1 .......................... 24 powe r- on reset (por) ............................................................. 25 reference clock inputs .............................................................. 26 monitor clock input .................................................................. 26 reference switching ................................................................... 26 reference monitor ...................................................................... 26 pll ............................................................................................... 27 output drivers ............................................................................ 28 output clocks ............................................................................. 28 applications information .............................................................. 29 dual - oscillator re ference input application ......................... 29 simple, single - oscillator reference input application ......... 30 interfacing to cmos clock outputs ....................................... 30 interfacing to lvds and hstl clock outputs ..................... 31 interfacing to hcsl clock outputs ........................................ 31 power supply ............................................................................... 32 power and grounding considerations and power supply rejection ...................................................................................... 32 outline dimensions ....................................................................... 33 ordering guide .......................................................................... 33 revision history 10 /14re vision 0: initial version rev. 0 | page 2 of 33
data sheet ad9574 specifications out0 channel absolute clock jitte r typical values applicable under the conditions of v s = 3. 3 v, t a = 25c, unless otherwise no ted . table 1 . parameter min typ max unit test conditions/comments high speed transceiver logic ( hstl ) integrated jitter j itter integration bandwidth = 12 khz to 5 mhz 19.44 mhz output 0. 196 ps r ms 25 mhz output 0. 179 ps r ms 38.88 mhz output 1. 943 ps r ms 50 mhz output 1. 523 ps r ms 3.3 v cmos integrated jitter j itter integration bandwidth = 12 khz to 5 mhz 19.44 mhz output 0. 204 ps r ms 25 mhz output 0. 178 ps r ms 38.88 mhz output 1. 969 ps r ms 50 mhz output 1. 446 ps r ms out1 channel absolute clock jitter typical values applicable under the conditions of v s = 3.3 v, t a = 25c, unless otherwise no ted . table 2 . parameter min typ max unit test conditions/comments hstl integrated jitter j itter integration bandwidth = 12 khz to 5 mhz 19.44 mhz output 0.175 ps rms 25 mhz output 0. 153 ps r ms 3.3 v cmos integrated jitter j itter integration bandwidth = 12 khz to 5 mhz 19.44 mhz output 0. 18 4 ps r ms 25 mhz output 0. 160 ps r ms out2 and out3 channels absolute clock jitte r typical values applicable under the conditions of v s = 3.3 v, t a = 25c, unless otherwise no ted. f requency multiplier ( 2) at pll input enabled . table 3 . parameter min typ max unit test conditions/comments hstl integrated jitter jitter integration bandwidth = 10 khz to 10 mhz 155.52 mhz output 0. 244 ps rms 156.25 mhz output 0. 234 ps r ms 160 mhz output 1. 290 ps rms frequency multiplier (2) at pll input bypassed jitter integration bandwidth = 12 khz to 20 mhz 155.52 mhz output 0.470 ps rms 156.25 mhz output 0. 243 ps r ms 160 mhz output 1. 329 ps r ms frequency multiplier ( 2 ) at pll input bypassed jitter integration bandwidth = 1.875 mhz to 20 mhz 155.52 mhz output 0. 409 ps r ms 156.25 mhz output 0.100 ps rms 160 mhz output 1. 257 ps r ms frequency multiplier ( 2 ) at pll input bypassed rev. 0 | page 3 of 33
ad9574 data sheet out4 and out 5 channels absolute clock jitte r typ ical values applicable under the conditions of v s = 3.3 v, t a = 25c . frequency multiplier ( 2) at pll input enabled unless otherwise indicated . table 4 . parameter min typ max unit test conditions/comments hstl integrated jitter input = c rystal o scillator jitter integration bandwidth = 10 khz to 10 mhz 38.88 mhz output 0.251 ps rms 77.76 mhz output 0.245 ps rms 80 mhz output 1.267 ps rms frequency multiplier ( 2 ) at pll input bypassed 100 mhz output 0.240 ps rms 125 mhz output 0.228 ps rms 160 mhz output 1.277 ps rms frequency multiplier ( 2 ) at pll input bypassed 312.5 mhz output 0.234 ps rms jitter integration bandwidth = 12 khz to 20 mhz 77.76 mhz output 0.488 ps rms 80 mhz output 1.314 ps rms frequency multiplier ( 2 ) at pll input bypassed 100 mhz output 0.252 ps rms 125 mhz output 0.233 ps rms 160 mhz output 1.321 ps rms frequency multiplier ( 2 ) at pll input bypassed 312.5 mhz output 0.236 ps rms jitter integrat ion bandwidth = 50 khz to 80 mhz 312.5 mhz output 0.389 ps rms jitter integration bandwidth = 1.875 mhz to 20 mhz 77.76 mhz output 0.430 ps rms 80 mhz output 1.242 ps rms frequency multiplier ( 2 ) at pll input bypassed 100 mhz output 0.115 ps rms 125 mhz output 0.089 ps rms 160 mhz output 1.248 ps rms frequency multiplier ( 2 ) at pll input bypassed 312.5 mhz output 0.072 ps rms high speed current sinking logic ( hcsl ) integrated jitter input= crystal oscillator jitt er integration bandwidth = 10 khz to 10 mhz 100 mhz output 0.238 ps rms 125 mhz output 0.226 ps rms 312.5 mhz output 0.240 ps rms jitter integration bandwidth = 12 khz to 20 mhz 100 mhz output 0.255 ps rms 125 mhz output 0.233 ps rms 312.5 mhz output 0.243 ps rms jitter integration bandwidth = 50 khz to 80 mhz 312.5 mhz output 0.445 ps rms jitter integration bandwidth = 1.875 mhz to 20 mhz 100 mhz output 0.131 ps rms 125 mhz output 0.098 ps rms 312. 5 mhz output 0.082 ps rms rev. 0 | page 4 of 33
data sheet ad9574 parameter min typ max unit test conditions/comments low voltage differential signaling ( lvds ) integrated jitter input = crystal oscillator jitter integration bandwidth = 10 khz to 10 mhz 38.88 mhz output 0.396 ps rms 77.76 mhz output 0.270 ps rms 80 mhz out put 1.304 ps rms frequency multiplier ( 2 ) at pll input bypassed 100 mhz output 0.247 ps rms 125 mhz output 0.234 ps rms 160 mhz output 1.314 ps rms frequency multiplier ( 2 ) at pll input bypassed 312.5 mhz output 0.246 ps rms jitter inte gration bandwidth = 12 khz to 20 mhz 77.76 mhz output 0.529 ps rms 80 mhz output 1.360 ps rms frequency multiplier ( 2 ) at pll input bypassed 100 mhz output 0.267 ps rms 125 mhz output 0.243 ps rms 160 mhz output 1.357 ps rms frequen cy multiplier ( 2 ) at pll input bypassed 312.5 mhz output 0.249 ps rms jitter integration bandwidth = 50 khz to 80 mhz 312.5 mhz output 0.473 ps rms jitter integration bandwidth = 1.875 mhz to 20 mhz 77.76 mhz output 0.474 ps rms 8 0 mhz output 1.289 ps rms frequency multiplier ( 2 ) at pll input bypassed 100 mhz output 0.149 ps rms 125 mhz output 0.109 ps rms 160 mhz output 1.284 ps rms frequency multiplier ( 2 ) at pll input bypassed 312.5 mhz output 0.082 ps rms o ut6 channel absolute clock jitte r typical values applicable under the conditions of v s = 3.3 v, t a = 25c, unless otherwise no ted. frequency multiplier ( 2) at pll input enabled. cycle to cycle jitter magnitude varies with respect to the clock edge (rising or falling). table 5 entries indica te jitter for the worst edge (rising or falling). the better edge typically offers a factor of 2 improvement over the tabulated jitter . table 5 . paramete r min typ max unit test conditions/comments lvds cycle to cycle jitter 1 000 cycles 66.6 mhz output 210 ps p -p 133.3 mhz output 353 ps p -p 1.8 v cmos cycle to cycle jitter 1000 cycles 66.6 mhz output 234 ps p -p 133.3 mhz output 363 ps p -p 3.3 v cmos cycle to cycle jitter 1000 cycles 33.3 mhz output 28 ps p -p 66.6 mhz output 207 ps p -p 133.3 mhz output 360 ps p -p rev. 0 | page 5 of 33
ad9574 data sheet clock output s (out0 _ x to out6 _ x ) static typical (t yp) is given for v s = 3.3 v 10%, t a = 25c, unless otherwise no ted. minimum ( min) and maximum (m ax) values are given over full v s and t a (? 40 c to + 85 c) variation. table 6 . parameter min typ max unit test conditions/comments hstl (out0 _x to out5 _x only ) 100 termination (differential) differential output voltage swing 7 45 955 1235 mv magnitude of volt age across pins; output driver static common - mode output voltage 745 950 1010 mv output driver static hcsl (out4 _x and out5 _x only ) 50 from each output pin to gnd differential output voltage swing 5 70 700 830 mv magnitude of voltage across pins; o utput driver static common - mode output voltage 295 360 430 mv output driver static lvds (out4 _x to out6 _x only ) 100 termination (differential) differential output voltage (v od ) 247 350 454 mv magnitude of voltage across pins; output driver static delta v od 50 mv output offset voltage (v os ) 1.125 1.25 1.375 v delta v os 50 mv short - circuit current (i sa , i sb ) 14 24 ma output shorted to gnd 1.8 v cmos (out6_x only ) output high voltage (v oh ) 1.7 v i load = 1 ma output low voltage ( v ol ) 0.1 v i load = 1 ma 3.3 v cmos (out0 _x , out1 _x, and out6 _x only ) output high voltage (v oh ) v dd 1 C 0.5 v i load = 10 ma output low voltage (v ol ) 0.5 v i load = 10 ma 1 v dd is the supply of all vdd_x pin s. clock output s (out0 _ x to out6 _ x ) dynamic typical (t yp) is given for v s = 3.3 v 10%, t a = 25c, unless otherwise no ted. minimum (min) and maximum (m ax) values are given over full v s and t a (?40c to +85c) variation. rise and fall time measurement thresholds are 20% and 80% of the nominal low and high amplitude of the wavefor m. table 7 . parameter min typ max unit test conditions/comments hstl (out1 _x to out5 _x only ) 100 termination (differential) out0 _x and out 1 _x measured differentially output rise time, t r l 161 195 232 ps output fall t ime, t f l 164 193 226 ps out2 _x to out5 _x measured differentially output rise time, t rp 114 144 175 ps output fall time, t fp 111 143 177 ps duty cycle out0 _x and out1 _x 45 55 % assumes 50% reference input duty cycle; duty cycle specificati on does not apply to out0 _x for 38.88 mhz and 50 mhz operation out2 _x to out5 _x 45 55 % hcsl (out4 _x and out5 _x only ) 50 from each output pin to gnd output rise time, t r l 195 206 221 ps measured differentially output fall time, t f l 188 211 238 ps measured differentially duty cycle 45 55 % rev. 0 | page 6 of 33
data sheet ad9574 parameter min typ max unit test conditions/comments lvds (out4 _x to out6 _x only ) 100 termination (differential) out4 _x , o ut5 _x output rise time, t rl 151 193 238 ps measured differentially output fall time, t fl 152 195 242 ps measured differentially out6 _x output rise time, t rl 221 242 273 ps measured differentially output fall time, t fl 224 241 270 ps measured differentially duty cycle out4 _x , out5 _x 45 55 % out6 _x 45 55 % 1.8 v cmos (out6_x only ) c load = 10 pf output rise time, t rc 1.2 1.7 ns output fall time, t fc 1.2 1.8 ns duty cycle 45 55 % 3.3 v cmos (out0 _x , out1 _x, and out6 _x o nly ) c load = 10 pf output rise time, t rc 0.5 1.0 ns output fall time, t fc 0.6 1.1 ns duty cycle out0 _x 45 55 % not applicable for 38.88 mhz and 50 mhz operation out1 _x 45 55 % out6 _x 45 55 % monitor clock inputs (mclk_ x) s tatic t ypical (t yp) is given for v s = 3.3 v 10%, t a = 25c, unless otherwise no ted. minimum (min) and maximum (m ax) values are given over full v s and t a (? 40 c to + 85 c) variation. table 8 . parameter min typ max unit test conditions/comments differential input mode common - mode internally generated bias voltage 1.192 v common - mode voltage tolerance 0.6 1. 5 v the accept able common - mode range for a 200 mv p - p dc - coupled input signal differential input capacitance 2 pf differential input resistance 5 k single - ended input cmos mode hysteresis 230 mv input resistance 1 m input capacitance 2 pf input high voltage 2 v input low voltage 1.2 v rev. 0 | page 7 of 33
ad9574 data sheet monitor clock input s (mclk_ x) dynamic typical ( t yp) is given for v s = 3.3 v 10%, t a = 25c, unless otherwise no ted. minimum ( m in) and maximum ( m ax) values are given over full v s and t a (?40c to + 85 c) variation. table 9 . parameter min typ max unit test conditions/comments differential input mode input sensitivity 1 00 mv p -p minimum input slew rate 5 0 v/s ensures proper device function when using a sinuso idal source duty cycle 40 60 % single - ended input cmos mode duty cycle 40 60 % reference input s (ref0 _x and ref 1 _ x ) static typical ( t yp) is given for v s = 3.3 v 10%, t a = 25c, unless otherwise no ted. minimum ( m in) and maximum ( m ax) values are given over full v s and t a (? 40 c to + 85 c) variation. table 10. parameter min typ max unit test conditions/comments differential input mode common - mode internally generated bias voltage 1.218 v common - mode voltage tolerance 0.650 1.8 v the acc eptable common - mode range for a 200 mv p -p dc - coupled input signal differential input capacitance 2 pf differential input resistance 4.3 k single - ended input cmos mode hysteresis 220 mv input resistance 1 m input capacitance 2 pf input high voltage 2 v input low voltage 1.2 v reference input s (ref0_ x and ref1_ x ) dynamic typical ( t yp) is given for v s = 3.3 v 10%, t a = 25c, unless otherwise no ted. minimum ( m in) and maximum ( m ax) values are given over full v s and t a ( ? 40 c to + 85 c) variation. table 11. parameter min typ max unit test conditions/comments differential input mode input sensitivity 2 00 mv p -p minimum input slew rate 100 v/s minimum limit imposed for jitter performan ce (when using a sinusoidal source, for example) duty cycle pll 2 multiplier bypass 40 60 % pll 2 multiplier active 40 60 % out0 2 multiplier active 40 60 % single - ended input cmos mode duty cycle pll 2 multiplier bypass 40 60 % pll 2 multiplier active 40 60 % out0 2 multiplier active 40 60 % ensures out0 _x duty cycle limits with out0 2 multiplier enabled rev. 0 | page 8 of 33
data sheet ad9574 reference switchover o utput disturbance typical ( t yp) is given for v s = 3.3 v 10%, t a = 25c, unless otherwi se no ted. minimum ( m in) and maximum ( m ax) values are given over full v s and t a (? 40 c to + 85 c) variation. table 12. parameter min typ max unit test conditions/comments instantaneous frequency (d /dt) disturbance due to referenc e switchover 250 5 00 ppm pk applies only to pll outputs ; 1 ppm frequency offset between the ref0 and ref1 channels instantaneous phase disturbance due to reference switchover 220 ps applies to out0 and out1 with out0 2 multiplier bypassed control pin s typical ( t yp) is given for v s = 3.3 v 10%, t a = 25c, unless otherwise no ted. minimum ( m in) and maximum ( m ax) values are given over full v s and t a (? 40 c to + 85 c) variation. table 13. parameter min typ max unit test conditions/comments input characteristics ref _ sel pin internal 30 k pull - down resistor logic 1 voltage (v ih ) 2.0 v logic 0 voltage (v il ) 0. 8 v logic 1 current (i ih ) 1 30 a v ih = v dd logic 0 current (i il ) 2 a v il = gnd reset pin internal 30 k pull - up resistor logic 1 voltage (v ih ) 2.0 v logic 0 voltage (v il ) 0.8 v logic 1 current (i ih ) 2 . 0 a v ih = v dd logic 0 current (i il ) 260 a v il = gnd refmon pin do not float this pin or toggle it during device operation ; c onnect to a static logic 0 or logic 1 logic 1 voltage (v ih ) v dd C 0.5 v logic 0 voltage (v il ) 0.5 v logic 1 current (i ih ) 9 5 a v ih = v dd logic 0 current (i il ) 95 a v il = gnd ppr 0 to ppr 6 pins maximum resistor tolerance = 10% ppr x state 0 820 pull - down to gnd ppr x state 1 1800 pull - down to gnd ppr x state 2 3900 pull - down to gnd ppr x state 3 8200 pull - down to gnd ppr x state 4 820 pull - up to v dd ppr x state 5 1800 pull - up to v dd ppr x state 6 3900 pull - up to v dd ppr x state 7 8200 pull - up to v dd rev. 0 | page 9 of 33
ad9574 data sheet status pins typical ( t yp) is given for v s = 3.3 v 10%, t a = 25c, unless otherwise no ted. minimum ( m in) and maximum ( m ax) values are given over full v s and t a (? 40 c to + 85 c) variation. table 14. parameter min typ max unit test conditions/comments output characteristics i load = 1 ma (source or sink) ld pin logic 1 voltage 2.0 v logic 0 voltage 0.8 v ref_act pin logic 1 voltage 2.0 v logic 0 voltage 0.8 v ref_sw pin logic 1 voltage 2.0 v logic 0 voltage 0.8 v ref_fhi pin internal 30 k pull - down resistor logic 1 voltage 2.0 v logic 0 voltage 0.8 v ref_flo pin internal 30 k pull - down resistor logic 1 voltage 2.0 v logic 0 voltage 0.8 v power supply and dissipation typical ( t yp) is given for v s = 3.3 v 10%, t a = 25c, unless otherwise no ted. minimum ( m in) and maximum ( m ax) values are given over full v s and t a (? 40 c to + 85 c) variation. table 15. parameter min typ max unit test conditions/comments power supply voltage 2.97 3.3 3.6 3 v power dissipation typical configuration 466 569 654 mw ppr 0 state 0 (ref0 _x : 25 mhz, 3.3 v cmos buffer; ref1 _x : no connection) ppr 1 state 0 (pll input 2 : off; out 2 : 156.25 mhz, hstl; out 3 : 156.25 mhz, hstl) ppr2 state 7 (out0: 25 mh z, hstl, 2 off; out 1 : disabled) ppr 3 state 0 (out 4 : 100 mhz, hstl; out 5 : 125 mhz, hstl) ppr 4 state 5 (out 6 : 66.67 mhz, 3.3 v cmos) ppr 5 state 0 (reference monitor threshold: not applicable ( 25 ppm)) ppr6 state 0 (mclk_x: no connect ion ( 19.44 mhz differential)) refmon: gnd all blocks running 579 698 803 mw ppr 0 state 4 (ref0 _x : 25 mhz, differential; ref1 _x : 25 mhz, differential) ppr1 state 0 (pll input 2: off; out2: 156.25 mhz, hstl; out3: 156.25 mhz, hstl) ppr2 state 2 (out 0 : 50 mhz, 3.3 v cmos, 2 on; out 1 : 25 mhz, 3.3 v cmos) ppr 3 state 2 (out 4 : 100 mhz, hcsl; out 5 : 125 mhz, hstl) ppr 4 state 1 (out 6 : 133.33 mhz, 3.3 v cmos) ppr 5 state 6 (reference monitor threshold: 100 ppm) ppr6 state 4 (mclk_x: 38.88 mhz, differential) refmon: v dd rev. 0 | page 10 of 33
data sheet ad9574 parameter min typ max unit test conditions/comments minimal power configuration 346 422 486 mw ppr0 state 0 (ref0 _x : 19.44 mhz, 3.3 v cmos buffer; ref1 _x : 19.44 mhz, 3.3 v cmos buffer) ppr1 state 4 (pll input 2: off, out2: 155.52 mhz, hstl; out3: 155.52 mhz, hstl) ppr 2 state 4 (out 0 : disabled; out 1 : disabled) ppr 3 state 7 (out 4 : disabled; out 5 : disabled) ppr 4 state 0 (out 6 : disabled) ppr 5 state 0 (reference monitor threshold: not applicable ( 25 ppm) ppr6 state 1 (mclk_ x: no connection ( 19.44 mhz, 3.3 v cmos buffer)) refmon: gnd incremental power dissipation typical configuration; values show the change in power due to the indicated operation input reference on/off applies to one reference clock input s ingle - ended 0.23 0.30 0.36 mw differential 20.5 25.1 30.0 mw output driver on/off lvds (at 312 . 5 mhz) 18.1 22.5 27.2 mw hstl (at 156.25 mhz) 30.6 36.6 42.5 mw 1.8 v cmos (at 66 mhz) 13.7 16.2 19.2 mw a single 1.8 v cmos output with an 10 pf l oad 3.3 v cmos (at 25 mhz) 9.5 12.2 15.2 mw a single 3.3 v cmos output with an 10 pf load other blocks on/off out 0 2 on/off 3.1 4.0 5.4 mw power supply current (i supply ) t otal supply current for vdd_x pins 1 in aggregate typical configuratio n 157 172 180 ma for power dissipation with typical configuration settings all blocks running configuration 195 212 221 ma for power dissipation with all blocks running configuration settings minimal power configuration 117 128 134 ma for power dissipati on with minimal power configuration settings 1 vdd_x pins include vdd_ref0, vdd_ref1, vdd_out01, vdd_pll, vdd_vco, vdd_rfdiv, vdd_out6, vdd_out4, vdd_out5, vdd_out23, and v dd_mclk. timing specification s typical (typ) is given for v s = 3.3 v 10%, t a = 25c, unless otherwise no ted. minimum (min) and maximum (max) values are given over full v s and t a (?40c to +85c) variation. the indic ated times assume the voltage applied to all 3.3 v power supply pins is within specification and stable. table 16. parameter min typ max unit test conditions/comments monitor clock input to ref_fhi/ref_flo time elapsed time fr om the first rising edge of the monitor clock input signal to the valid reference status as indicated by the ref_f hi and ref_f lo pins (the active reference must be stable) f mclk = 8 khz 4200 ms f mclk = 10 mhz 3400 ms f mclk = 19.44 mhz 1800 ms f mclk = 25 mhz 1400 ms f mclk = 38.88 mhz 870 ms rev. 0 | page 11 of 33
ad9574 data sheet parameter min typ max unit test conditions/comments output ready time out0 to out 1 0.2 ms typical start - up time of the external crystal oscillator dominates the output ready time of the out0 and out1 channels out2 to out 6 time interval fro m reset pin = logic 1 to ld pin = logic 1 (pll lock detection) ppr 1 state 0 5.0 ms ppr 1 state 1 2.8 ms ppr 1 state 2 5.0 ms ppr 1 state 3 2.8 ms ppr 1 state 4 6.4 ms ppr 1 state 5 3.6 ms ppr 1 state 6 22.3 ms ppr1 state 7 11.5 ms timing diagrams figure 2. cmos timing, single - ended, 10 pf load figure 3. lvds, hstl, hcsl timing, differential single-ended cmos 10pf load 80% 20% t rc t fc 07501-002 differential lvds/hstl/hcsl 80% 20% t rl t fl 07501-003 rev. 0 | page 12 of 33
data sheet ad9574 absolute maximum rat ings table 17. parameter rating vdd_x to gnd ? 0.3 v to + 3.6 v junction temperature 1 150 c storage temperature range ?65 c to + 150c 1 see table 18 for ja . stresses at or above those listed under absolute maximum ratings may cause permanent damage to the p roduct. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. thermal impedance is based on a 4 - layer board in still air in accordance with jedec jesd 51 - 7 plus jedec jesd 51 - 5 2s2p test board and i n accordance with jedec jesd51 - 2 (still air) . table 18. thermal resistance package type ja unit 48 - lead , 7 mm 7 mm lfcsp 32.6 c/w esd caution rev. 0 | page 13 of 33
ad9574 data sheet pin configuration an d function descripti ons figure 4. pin configuration table 19. pin function description s pin no. mnemonic input/ output pin type description 1 ref 0 _p i nput configurable clock input reference clock input 0 , positive . c onfigura ble via ppr0 ( pin 47) . 2 ref 0 _n in put configurable clock input reference clock input 0 , negative . configurable via ppr0 ( pin 47). 3 vdd_ref0 input power 3.3 v input supply for reference clock input 0 (ref0_x) . this pin suppl ies the single - ended input receiver and internal low dropout ( ldo ) regulator for the differential receiver . 4 vdd_ref 1 input power 3.3 v input supply for reference clock input 1 (ref1_x) . this pin suppl ies the single - ended input receiver and internal ldo regulator for the differential receiver. 5 ref 1 _n input configur able clock input reference clock input 1 , negative . configurable via ppr0 ( pin 47) . 6 ref 1 _p input configurable clock input reference clock input 1 , positive . configurable via ppr0 ( pin 47). 7 ppr2 input control pin program reader 2. connect a resistor t o this pin to configure the out0 and out1 channels (see the ppr2 out0 and out1 configuration section for more information ) . 8 vdd_out 01 input power 3.3 v supply . 3.3 v input for the cmos d rivers of out0 _x and out1 _x and the source for an internal 1.8 v ldo regulator for the differential drivers of out0 _x and out1 _x . 9 out0_n o utput configurable clock output clock output 0 , negative . configurable via ppr2 ( pin 7). 10 out 0 _p output configurable clock output clock o utput 0 , positive . configurable via ppr2 ( pin 7). 11 out 1 _p output configurable clock output clock output 1 , positive . configurable via ppr2 ( pin 7). 12 out 1 _n output configurable clock output clock output 1 , negative . configurable via ppr2 ( pin 7). 13 vdd_pll input power 3.3 v input to the internal ldo regulator for the pll. 14 ld output 3.3 v cmos pll lock detector status. logic 0 = unlocked; logic 1 = l ocked . 15 lf i nput /o utput analog loop filter. connect a capacitor or series r c network (see table 33 ) from this pin to ld o _byp ( pin 1 6 ). 1 2 ad9574 t o p view (not to scale) 3 4 5 6 7 24 23 22 21 20 19 18 17 16 15 14 13 44 45 46 47 48 43 42 41 40 39 38 37 25 26 27 28 29 30 31 32 33 34 35 36 8 9 10 1 1 12 07501-004 ref0_p vdd_ref0 ref0_n vdd_ref1 ref1_p ref1_n ppr2 vdd_out01 out0_n out0_p out1_p out1_n vdd_pll ld lf ldo_byp vdd_vco ppr6 reset vdd_rfdiv out6_p out6_n vdd_out6 ppr5 refmon ppr4 ppr3 out4_p out4_n vdd_out4 vdd_out5 out5_n out5_p ref_flo ref_fhi vdd_out23 out2_p out2_n out3_n out3_p ppr1 vdd_mclk ref_sw ref_act mclk_n mclk_p ppr0 ref_sel notes 1. the exposed die pad must be connected to the power supply common (gnd). rev. 0 | page 14 of 33
data sheet ad9574 rev. 0 | page 15 of 33 pin no. mnemonic input/ output pin type description 16 ldo_byp output analog ldo bypass. connect a 470 nf capacitor from this pin to gnd. 17 vdd_vco input power 3.3 v supply. 3.3 v input to the internal ldo regulator for the vco. 18 vdd_rfdiv input power 3.3 v supply. 3.3 v input to the internal ldo regulator for the vco rf dividers. 19 ppr6 input control pin program reader 6. connect a resistor to this pin to configure the mclk_x input (see the ppr6monitor clock (mclk _x) input configuration section for more information). 20 reset input 3.3 v cmos reset. logic 0 (gnd) initializes the device to its default state (see the pprx pins section for details). this pin has an internal 30 k pull-up resistor. 21 out6_n output configurable clock output clock output 6, negative. configurable via ppr4 (pin 26). 22 out6_p output configurable clock output clock output 6, positive. configurable via ppr4 (pin 26). 23 vdd_out6 input power 3.3 v supply. 3.3 v input for the cmos drivers of out6_x and the source for an internal 1.8 v ldo regulator for the 1.8 v cmos drivers and differential drivers of out6_x. 24 ppr5 input control pin program reader 5. connect a resistor to this pin to configure the reference clock frequency error threshold (see the ppr5reference monitor threshold section for more information). 25 refmon input control reference frequency monitor enable/disable . do not float this pin or toggle it during device operation. be sure to connect it to a static logic 0 or logic 1. 26 ppr4 input control pin program reader 4. connect a resistor to this pin to configure the out6 channel (see the ppr4out6 configuration section for more information). 27 ppr3 input control pin program reader 3. connect a resistor to this pin to configure the out4 and out5 channels (see the ppr3out4 and out5 configuration section for more information). 28 out4_n output configurable clock output clock output 4, negative. configurable via ppr3 (pin 27). 29 out4_p output configurable clock output clock output 4, positive. configurable via ppr3 (pin 27). 30 vdd_out4 input power 3.3 v supply. 3.3 v input for an internal 1.8 v ldo regulator for the differential drivers of out4_x. 31 vdd_out5 input power 3.3 v supply. 3.3 v input for an internal 1.8 v ldo regulator for the differential drivers of out5_x. 32 out5_p output configurable clock output clock output 5, positive. configurable via ppr3 (pin 27). 33 out5_n output configurable clock output clock output 5, negative. configurable via ppr3 (pin 27). 34 ref_flo output 3.3 v cmos low reference frequency status indicator. a logic 1 indicates that the reference frequency is below the lower threshold limit (see the reference monitor section for details). this pin is an open-drain output with an internal 30 k pull-down resistor. 35 ref_fhi output 3.3 v cmos high reference frequency status indicator. a logic 1 indicates that the reference frequency is above the upper threshold limit (see the reference monitor section for details). this pin is an open-drain output with an internal 30 k pull-down resistor. 36 vdd_out23 input power 3.3 v supply. 3.3 v input for an internal 1.8 v ldo regulator for the differential drivers of out2_x and out3_x. 37 out2_n output configurable clock output clock output 2, negative (hstl). configurable via ppr2 (pin 7). 38 out2_p output configurable clock output clock output 2, positive (hstl). configurable via ppr2 (pin 7). 39 out3_p output configurable clock output clock output 3, positive (hstl). configurable via ppr2 (pin 7). 40 out3_n output configurable clock output clock output 3, negative (hstl). configurable via ppr2 (pin 7).
ad9574 data sheet rev. 0 | page 16 of 33 pin no. mnemonic input/ output pin type description 41 ppr1 input c on t ro l pin program reader 1. connect a resistor to this pin to select a predefined frequency translation configuration (see the ppr1frequency translation settings section for more information). 42 vdd_mclk input power 3.3 v supply. 3.3 v input for reference monitor clock 0 (mclk_x). this pin supplies the single-ended input receiver and internal ldo regulator for the differential receiver. 43 ref_sw output 3.3 v cmos reference switchover status indicator. this pin indicates when the device is in the process of switching references (see the reference monitor section for more information). 44 ref_act output 3.3 v cmos reference active status indicator. this pin indicates whether ref0 or ref1 is the active reference (see the reference monitor section for more information). 45 mclk_p input configurable monitor clock input reference monitor clock normal input. configurable via ppr6 (pin 18). 46 mclk_n input configurable monitor clock input reference monitor clock complementary input. configurable via ppr6 (pin 18). 47 ppr0 input control pin program reader 0. connect a resistor to this pin to configure the reference clock inputs (see the ppr0reference clock input configuration section for more information). 48 ref_sel input 3.3 v cmos reference clock select. the pin selects input reference clock 0 or input reference clock 1 as the internal reference clock source (logic 0 or logic 1, respectively). this pin has an internal 30 k pull-down resistor. ep i nput gnd exposed pad. the exposed die pad must be connected to the power supply common (gnd). ?
data sheet ad9574 typical performance characteristics phase noise and volt age waveform s v dd = nominal , t a = 25c . the only enabled output channels are those indicated in the figure caption s. t he phase noise plots (see figure 5 to figure 9 ) show t he taitien xo a0145 - l - 006 - 3 phase noise normalized to the output frequency. the voltage waveform plots (see figure 10 to figure 16 ) embody ac coupling to the measurement instrument. figure 5. phase noise ( out0) f out0 = 25 mhz figure 6. phase noise (out4) f out4 = 100 mhz, f out5 = 125 mhz figure 7. phase noise (out4) f out4 = 312.5 mhz figure 8. phase noise (out2) f out2 = 15 6.25 mhz figure 9. phase noise (out5 ) f out4 = 100 mhz, f out5 = 125 mhz figure 10 . output waveform, hstl (25 mhz, 312.5 mhz) ?110 ?170 ?160 ?150 ?140 ?130 ?120 100 1k 10k 100k 10m 1m phase noise (dbc/hz) frequency offset (hz) 07501-005 taitien xo a0145-l-006-3 cmos 3.3v hstl rms jitter hstl: 0.197ps cmos: 0.195ps integr a tion bandwidth: 12khz t o 20mhz ?100 ?170 ?160 ?150 ?140 ?130 ?120 100 1k 10k 100k 10m 1m phase noise (dbc/hz) frequency offset (hz) 07501-006 100m ?110 taitien xo a0145-l-006-3 hcsl hstl rms jitter hstl: 0.245ps hcsl: 0.244ps integr a tion bandwidth: 12khz t o 20mhz ?90 ?160 ?150 ?140 ?130 ?120 ?110 100 1k 10k 100k 10m 1m phase noise (dbc/hz) frequency offset (hz) 07501-007 100m ?100 rms jitter hstl: 0.230ps hcsl: 0.245ps l vds: 0.254ps integr a tion bandwidth: 12khz t o 20mhz taiten xo a0145-l-006-3 hcsl hstl lvds ?100 ?170 ?160 ?150 ?140 ?130 ?120 100 1k 10k 100k 10m 1m phase noise (dbc/hz) frequency offset (hz) 07501-008 100m ?110 rms jitter hstl: 0.234ps integr a tion bandwidth: 12khz t o 20mhz taitien xo a0145-l-006-3 hstl ?100 ?170 ?160 ?150 ?140 ?130 ?120 100 1k 10k 100k 10m 1m phase noise (dbc/hz) frequency offset (hz) 07501-009 100m ?110 rms jitter hstl: 0.228ps integr a tion bandwidth: 12khz t o 20mhz taitien xo a0145-l-006-3 hstl 1.25 ?1.25 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 0 5 10 15 20 25 30 35 40 45 50 output voltage (v) time (ns) 07501-010 312.5mhz 25mhz rev. 0 | page 17 of 33
ad9574 data sheet figure 11 . output waveform, hcsl (10 0 mhz, 31 2.5 mhz) figure 12 . output waveform, 1.8 v cmos (66.67 mhz ) figure 13 . output waveform, 1.8 v cmos (133.3 mhz) figure 14 . output waveform, lvds ( 66.67 mhz, 312.5 mhz) figure 15 . output waveform, 3.3 v cmos (25 mhz) figure 16 . output waveform, 3.3 v cmos (133.3 mhz) 1.00 ?1.00 ?0.75 ?0.25 0.25 output voltage (v) 07501-011 0.75 ?0.50 0.50 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 time (ns) 312.5mhz 100mhz 1.0 ?1.0 ?0.5 0 0.5 0 30 25 20 15 10 5 output voltage (v) time (ns) 07501-012 66.67mhz, 2pf_p 66.67mhz, 2pf_n 66.67mhz, 10pf_p 66.67mhz, 10pf_n 1.0 0.5 0 ?1.0 ?0.5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 output voltage (v) time (ns) 07501-013 133.3mhz, 2pf_p 133.3mhz, 2pf_n 133.3mhz, 10pf_p 133.3mhz, 10pf_n 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 30 25 20 15 10 5 output voltage (v) time (ns) 07501-014 66.67mhz 312.5mhz 2.5 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 output voltage (v) time (ns) 07501-315 25mhz, 2pf_p 25mhz, 10pf_p 25mhz, 2pf_n 25mhz, 10pf_n 2.5 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 5 10 15 20 output voltage (v) time (ns) 07501-316 133.3mhz, 2pf_p 133.3mhz, 10pf_p 133.3mhz, 2pf_n 133.3mhz, 10pf_n rev. 0 | page 18 of 33
data sheet ad9574 reference switching frequency and phase disturbance v dd = nominal, t a = 25c. the only enab led output channels are those indicated in the figure caption s. the reference switchover phase disturbance plots ( figure 18 and figure 19 ) each show a collection of output phase variations due to approximately 250 reference switching events between two references with a frequency offset of approximately 2 ppm. each reference switch event (initiated by toggl ing the ref_sel pin) occurs at a random phase offset between the two references. the plots demonstrate the tightly controlled phase disturbance at the output as a result of the reference switching logic seeking the optimal moment to switch references. figure 17 . reference switchover frequency di sturbance for out2 at 156.25 mhz (ppr0 = 0, ppr1 = 1, ppr2 = 2, ppr3 = 0, ppr4 = 0, ppr5 = 0, ppr6 = 2) figure 18 . reference switchover phase disturbance for out3 at 156.25 mhz (ppr0 = 0, ppr1 = 1, ppr2 = 3, ppr3 = 2, ppr4 = 1 , ppr5 = 7, ppr6 = 7) figure 19 . reference switchover phase disturbance for out0 at 25 mhz with output 2 multiplier bypassed (ppr0 = 0, ppr1 = 1, ppr2 = 3, ppr3 = 2, ppr4 = 1, ppr5 = 7, ppr6 = 7) ?45000 frequency deviation (hz) 07501-113 ?40000 ?35000 ?30000 ?25000 ?20000 ?15000 ?10000 ?5000 0 5000 15000 20000 25000 30000 35000 40000 45000 50000 ?1.5 ?0.5 0.5 1.5 2.5 rel a tive time ( s) ?1 ppm reference frequency offset +1 ppm reference frequency offset relative phase (degrees) 07501-115 0 5 6 7 ?0.2 0 rel a tive time ( s) 2 3 4 1 ?3 ?2 ?1 ?6 ?5 ?4 ?7 ?0.1 0.1 0.3 0.2 10 degrees 1 degree = 17.78ps 2.0 1.0 0 ?1.0 ?2.0 ?0.2 ?0.1 0 0.1 0.2 07501-215 relative phase (degrees) relative time (s) 0.3 ?1.5 ?0.5 0.5 1.5 1.5 degrees 1 degree = 111.1ps rev. 0 | page 19 of 33
ad9574 data sheet terminology phase jitter an ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 for each cycle. actual signals, however, display a certain amount of variation from ideal phase progression over time. this phenomenon is c alled phase jitter. although many causes can contribute to phase jitter, one major cause is random noise, which is char acterized statistically as gaussian (normal) in distribution. this phase jitter leads to the energy of the sine wave spreading out in th e frequency domain, producing a continuous power spectrum. this power spectrum is usually reported as a series of values whose units are dbc/hz at a given offset in frequency from the sine wave (carrier). the value is a ratio (expressed in db) of the power contained within a 1 hz bandwidth with respect to the power at the carrier frequency. for each measurement, the offset from the carrier frequency is also given. phase noise when the total power contained within some interval of off set frequencies (for ex ample, 12 khz to 2 0 mhz) is integrated, it is called the integrated phase noise over that frequency offset interval , and it can be readily related to the time jitter due to the phase noise within that offset frequency interval. phase noise has a detrimenta l effect on error rate performance by increas ing eye closure at the transmitter output and reducing the jitter tolerance/sensitivity of the receiver. time jitter phase noise is a frequency domain phenomenon. in the time domain, the same effect is exhibite d as time jitter. when observing a sine wave, the time of successive zero crossings is seen to vary. in a square wave, the time jitter is seen as a displacement of the edges from their ideal (regular) times of occurrence. in both cases, the variations in t iming from the ideal are the time jitter. because these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the gaussian distribution. additive phase noise additive phase noise is the amoun t of phase noise that is attributable to the device or subsystem being measured. the phase noise of any external oscillators or clock sources is subtracted. this makes it possible to predict the degree to which the device impacts the total system phase noi se when used in conjunction with the various oscillators and clock sources, each of which contribute s its own phase noise to the total. in many cases, the phase noise of one element dominates the system phase noise. additive time jitter additive time jitte r is the amount of time jitter that is attributable to the device or subsystem being measured. the time jitter of any external oscillators or clock sources is subtracted. this makes it possible to predict the degree to which the device impact s the total sy stem time jitter when used in conjunction with the various oscillators and clock sources, each of which contribute s its own time jitter to the total. in many cases, the time jitter of the external oscillators and clock sources dominates the system time jit ter. rev. 0 | page 20 of 33
data sheet ad9574 theory of operation figure 20 . detailed block diagram overview figure 20 shows a block diagram of the ad9574 . the ad9574 accepts a 19.44 mhz or 25 mhz reference clock at the ref0 _x and/or r ef1 _x inputs. it also accepts a 0.008 mhz , 10 mhz , 19.44 mhz , 25 mhz , or 38.88 mhz monitor input clock at the mclk _x input. t he monitor input clock serves as a stable frequency reference for the internal reference frequency monitor of the device . the input clock receivers provide differential or single - ended input configurations . the ad9574 provides up to seven output channel clocks (out0 to out6). the out0 and out1 channels provide a replica of the ref0 or ref1 channel frequency with a frequency doubling option for out0. the out2 through out6 channels provide various ou tput frequencies by means of an integrated pll and divider chains. the output clock drivers provide for a variety of modes including lvds, hstl, hcs l, 1.8 v cmos , and 3.3 v cmos, al though not all modes are available at every output. the integrated pll prov ides the necessary frequency translations. the divider block at the input to the pll consists of a 2 multiplier, a divide - by - 5, and a multiplexer configured to provide the four possible divide values (1/2, 1, 5/2, or 5), as shown in figure 20 . ppr x pins the ad9574 makes use of seven pprx pins to configure the device . internal circuitry scans the ppr x pins for the presence of resistor terminations and confi gures the device accordingly . a ppr x pin scan occurs automatically as part of the power - on reset sequence (see the power - on reset (por) section) or following assertion of the reset pin. each ppr x pin controls a specific function or functional block within the device (see table 20) . the configuration of a functional block depends on the scanned state of the corresponding ppr x pin . the scan of a ppr x pin iden tifies one of eight possible states based on an external pull - up or pull - do wn resistor (maximum 10% tolerance) per table 21 . pll ref0_p ref0_n ref1_p ref1_n mclk_p mclk_n reference frequency monitor ref_act ref_sw ref_fhi ref_flo ref. switch ref_sel ppr control ppr3 ppr4 ppr5 ppr6 ppr0 ppr1 ppr2 1/2, 1, 5/2, 5 pfd cp loop filter lock det vco ld lf 50, 64, 100, 128, 256, 512 reset reset out0_n out0_p 3.3v cmos hstl 3.3v cmos 2 a a out1_n out1_p out2_n out2_p out3_n out3_p hstl hstl out4_n out4_p lvds/hcsl/hstl out5_n out5_p lvds/hcsl/hstl 8 out6_p out6_n 3.3v cmos lvds 3.3v cmos 1.8v cmos 1.8v cmos 2, 4, 5, 8, 16 3.75 2 2 2488mhz 2500mhz 2560mhz refmon 4 5 ad9574 07501-015 1 48 2 25 44 43 35 34 6 5 47 41 7 27 26 24 19 20 14 15 22 21 29 28 32 33 38 37 39 40 10 9 11 12 46 45 rev. 0 | page 21 of 33
ad9574 data sheet table 20. ppr x pin function assignments mnemonic pin n o. functio n assignment ppr0 47 reference input configuration ppr1 41 frequency translation settings ppr 2 7 out0 and out1 channel configuration ppr 3 27 out4 and out5 channel configuration ppr 4 26 out6 channel configuration ppr 5 24 reference clock frequency moni tor error threshold ppr 6 19 monitor clock (mclk _x ) input configuration device programming consists of connecting the appropriate value programming resistors to the ppr x pins and terminating the resistors to v dd or gnd (per table 21 ). for example, figure 21 shows how to program ppr0 to state 3 . table 21. ppr x state ppr x state resistance terminus 0 820 gnd 1 1.8 k gnd 2 3.9 k gnd 3 8.2 k gnd 4 820 v dd 5 1.8 k v dd 6 3.9 k v dd 7 8.2 k v dd figure 21 . ppr x programming resistor example for details regarding the device configuration based on the scanned ppr x st ates, refer to the description of each ppr x pin in the following sections. ppr0 reference clock input configuration the ppr0 pin controls the configuration of the reference clock inputs ( ref0 _x and ref1 _x ) . the selected ppr0 state app lies to both referenc es (ref0 _x and ref1 _x ). table 22 associates each ppr0 state with a particular reference input configuration. table 22. ppr0 reference input options ppr 0 state reference clock input configur ation 0 single - ended 3.3 v cmos buffer 1 not applicable 2 not applicable 3 not applicable 4 differential 5 not applicable 6 not applicable 7 not applicable ppr1 frequency translation s ettings the ppr1 pin allows the user to select from a predefine d set of frequency translation groups per table 23 (with all frequency entries in mhz) . the frequency translations apply to the out4 and out5 channels with respect to the reference frequency (f ref ) at the ref0 _x or ref1 _x inputs . this also establishes the frequency at the out2 and out3 channels as shown in table 23. note that the frequency translation associated with each ppr x state relies on one of three possible vco freque ncies shown in table 23. the 2 column in table 23 indicates the status of the 2 multiplier associated with the divider at the input to the pll (as explained in the overview section). the pll bandwidth column indicates the ? 3 db cl osed - loop bandwidth of the pll. the frequency group for a given ppr1 state defines a pair of out4 and out5 frequencies. the frequency pair associated with a ppr1 state may apply to the out4 or out5 channel in any combination. for example, although ppr1 state 0 defines both 100 mhz and 125 mhz output frequencies, out4 and out5 may be any pairing of the two freq uencies: 100 mhz at both output channels , 100 mh z on out4 and 125 mhz at out5, 125 mhz at out4 and 100 mhz at out5 , or 125 mhz at both output channels . the specific out4 and out5 fre - quency assignments depend on the state of ppr3 (see table 25 ). see the output clocks section for details for the specific frequency translations on a per output basis. table 23. ppr1 frequency translation options ppr 1 state f ref (mhz) out4/ out 5 frequency (mhz) 2 pll bandwidth (mhz) f vco out2/ out 3 frequency (mhz) 0 25 100, 125 bypass 0. 7 2500 156.25 1 25 100,125 active 0. 6 2500 156.25 2 25 125, 312.5 bypass 0. 7 2500 156.25 3 25 125, 312.5 active 0. 6 2500 156.25 4 19.44 38.88 , 77.76 bypass 0.6 2488 155.52 5 19.44 38.88 , 77.76 active 0.6 2488 155.52 6 25 80, 160 bypass 0.3 2560 160 7 25 80, 160 active 0.6 2560 160 ppr0 8.2 k? ad9574 07501-016 47 rev. 0 | page 22 of 33
data sheet ad9574 ppr2 out0 and out1 configuration the ppr2 pin allows the user to select from a predefined set of configurations for the out 0 and out 1 channels per table 24. the output configuration includes the type of output driver and a frequency scale factor that indicates whether the output frequency is the same or twice the input reference frequency. see the output drivers section for details regarding output driver types. ppr3 out4 and out5 configuration the ppr3 pin allows the user to select from a predefined set of configurations for the out4 and out5 channels per table 25. the output configuration includes the frequency ( in mhz) and type of output driver assignment (see the output drivers section for details regarding output driver types). note t hat the state of ppr1 (frequency translation options) determines the frequency pair available for assignment to the out4 and out5 channels . table 24 . ppr2 out0/out1 options ppr2 state out0 out1 driver scale driver scale 0 hstl 1 hstl 1 1 hstl 2 hstl 1 2 3.3 v cmos 2 3.3 v cmos 1 3 3.3 v cmos 1 3.3 v cmos 1 4 disabled not applicable disabled not applicable 5 3.3 v cmos 1 disabled not applicable 6 hstl 2 disabled not applicable 7 hstl 1 disabled not applicable table 25. ppr3 out4/out5 options ppr state out4 out5 ppr1 ppr3 driver f out4 (mhz) driver f out5 (mhz) 0 or 1 0 hstl 100 hstl 125 1 hcsl 100 hcsl 100 2 hcsl 100 hstl 125 3 lvds 125 lvds 125 4 hstl 125 hstl 125 5 lvds 100 hcs l 100 6 h stl 100 hstl 100 7 disabled not applicable disabled not applicable 2 or 3 0 hstl 312.5 hstl 312.5 1 lvds 312.5 lvds 312.5 2 hcsl 312.5 hcsl 312.5 3 hstl 312.5 hstl 125 4 lvds 312.5 lvds 125 5 hcsl 312.5 hcsl 125 6 lvds 312.5 hstl 125 7 hcs l 125 hcsl 125 4 or 5 0 hstl 38.88 hstl 77.76 1 lvds 38.88 lvds 77.76 2 lvds 38.88 lvds 38.88 3 hstl 38.88 hstl 38.88 4 hstl 77.76 hstl 77.76 5 lvds 77.76 lvds 77.76 6 disabled not applicable hstl 38.88 7 disabled not applicable disabled not applicable 6 or 7 0 hstl 80 hstl 80 1 lvds 80 hstl 80 2 lvds 8 0 lvds 160 3 disabled not applicable hstl 80 4 lvds 80 lvds 80 5 hstl 80 hstl 160 6 disabled not applicable hstl 160 7 disabled not applicable disabled not applicable rev. 0 | page 23 of 33
ad9574 data sheet ppr4 out6 configuration the ppr4 pin allows the user to select from a predefined set of configurations for the out6 channel per table 26 . the output configura tion includes the frequency (mhz) and type of output driver assi gnment (see the output drivers section for details regarding output driver types). note that the ppr4 assignments share a dependency with the state of ppr1 (frequency translation options) in that the out6 channel i s disa bled for ppr1 state 2 through state 7. table 26. ppr4 out6 options ppr state out 6 ppr1 ppr4 driver f out 6 mh 0 or 1 0 disabled not applicable 1 3.3 v cmos 133.3 2 1.8 v cmos 133.3 3 lvds 133.3 4 lvds 66 .67 5 3.3 v cmos 66 .67 6 1.8 v cmos 66 .67 7 3.3 v cmos 33.33 2 to 7 0 to 7 disabled n ot applicable ppr5 reference monitor threshold the ppr5 pin controls the range of the frequency error threshold associated with the reference frequency monitor (see the reference monitor section) per table 27. the threshold has units of parts per million (ppm) relative to the nominal input reference frequency (19.44 mhz or 25 mhz) . table 27. ppr5 reference monitor threshold options ppr 5 state threshold ppm 0 25 1 25 2 10 3 10 4 50 5 50 6 100 7 100 ppr6 monitor clock (mclk _x ) input configuration the ppr6 pin controls the configuration of the mclk _ x input s , which includes a combination of both frequency (mhz) and input type (see the monitor clock input section for details regarding mclk _x input types). table 28 assoc iates each ppr6 state with a particular mclk _x input configuration. table 28. ppr6 mclk _x input options ppr 6 state f mclk mh mclk _x input configuration 0 19.44 differential 1 19.44 single - ended 3.3 v cmos buffer 2 0.008 single - ended 3.3 v cmos buffer 3 0.008 differential 4 38.88 differential 5 25 differential 6 10 single - ended 3.3 v cmos buffer 7 10 differential dependency of ppr3 and ppr 4 on ppr1 ppr1 define s the input reference frequency, configures the internal pll to y ield certain out2 and out3 frequencies and establishes the state of the 2 multiplier at the input of the pll (bypass/active ). ppr3 and ppr4 affect the frequency and output driver of the out4, out5 , and out6 channels , but with a dependency on the state of ppr1 as summarized in table 29 . with regard to table 29 , the user may select any ppr3 state and any ppr4 state for a given ppr1 state (that is, ppr3 and ppr4 are completely independent of one another). rev. 0 | page 24 of 33
data sheet ad9574 table 29. ppr1, ppr3 , and ppr4 dependencies 1 ppr 1 state f ref (mhz) pll 2 out2/ out 3 freq. (mhz) ppr 3 state out 4 out 5 ppr 4 state out 6 freq. (mhz) driver freq. (mhz) driver fre q . (mhz) driver 0 25 bypass 156.25 0 100 hstl 125 hstl 0 n/a disabled 1 25 active 156.25 1 100 hcsl 100 hcsl 1 133.3 3.3 v cmos 2 100 hcsl 125 hstl 2 133.3 1.8 v cmos 3 125 lvds 125 lvds 3 133.3 lvds 4 125 hstl 125 hstl 4 66.67 lvds 5 100 lvds 100 hcsl 5 66.67 3.3 v cmos 6 100 hstl 100 hstl 6 66.67 1.8 v cm os 7 n/a disabled n/a disabled 7 33.33 3.3 v cmos 2 25 bypass 156.25 0 312.5 hstl 312.5 hstl 0 n/a disabled 3 25 active 156.25 1 312.5 lvds 312.5 lvds 1 n/a disabled 2 312.5 hcsl 312.5 hcsl 2 n/a disabled 3 312.5 hstl 125 hstl 3 n/a disabled 4 312.5 lvds 125 lvds 4 n/a disabled 5 312.5 hcsl 125 hcsl 5 n/a disabled 6 312.5 lvds 125 hstl 6 n/a disabled 7 125 hcsl 125 hcsl 7 n/a disabled 4 19.44 bypass 155.52 0 38.88 hstl 77.76 hstl 0 n/a disabled 5 19.44 active 155.52 1 38.88 lvds 77.76 lvds 1 n/a disabled 2 38.88 lvds 38.88 lvds 2 n/a disabled 3 38.88 hstl 38.88 hstl 3 n/a disabled 4 77.76 hstl 77.76 hstl 4 n/a disabled 5 7 7.76 lvds 77.76 lvds 5 n/a disabled 6 n/a disabled 38.88 hstl 6 n/a disabled 7 n/a disabled n/a disabled 7 n/a disabled 6 25 bypass 160 0 80 hstl 80 hstl 0 n/a disabled 7 25 active 160 1 80 lvds 80 hstl 1 n/a disabled 2 80 lvds 160 lvds 2 n/a disabled 3 n/a disabled 80 hstl 3 n/a disabled 4 80 lvds 80 lvds 4 n/a disabled 5 80 hstl 160 hstl 5 n/a disabled 6 n/a disabled 160 hstl 6 n/a disabled 7 n/a disabled n/a disabled 7 n/a disabled 1 n/a = not applicable. power - o n reset (por) applyin g power to the ad9574 causes an interna l power - on reset (por) event . a por event allows the device to initialize to a known state at power - up by initiating a scan of the ppr x pins (see the pprx pins section). in general, the ad9574 follows an orderly power - on sequence beginning with the por circuit detecting a valid 3.3 v supply. this activates the internal ldo regulators. detection of valid ldo voltages by the por circuit triggers a ppr x scan sequence, which results in the configuration of the input reference receivers. assuming the presence of the active reference, the reference signal appears at the input to the pll and at the out0 and out1 channels . with a reference signal applied to the input of the pll , the vco calibration sequence initiates. assuming a valid input reference signal, the pll eventually locks to the reference signal as indicated by assertion of the ld pin. this lock enables the prescale dividers at the output of the vco , which starts the output drivers toggling (that is, those output drivers enabled per the ppr x settings). rev. 0 | page 25 of 33
ad9574 data sheet reference clock inpu ts the ref0 and ref1 input channel s pr ovide for two operating modes based on the scanned state of ppr0. note that t he resulting mode applies to both the ref0 and ref1 channel s. that is, independent input mode selection is not an option. in single - ended 3.3 v cmos buffer mode, the user may conn ect a 3.3 v clock source directly to the positive reference i nput pin (ref0_p, for example). note that in single - ended mode , it is best to connect a 0.1 nf capacitor from the negative input pin (ref0_n, for example) to gnd. in differential mode, the user may connect a differential clock driver to the two reference inpu t pins (ref0_p and ref0 _n, for example). note that differential operation requires ac coupling , that is, a series connected 0.1 nf capacitor from each output of an external differential clock driver to the corresponding reference input pin. this mode also supports a single - ended 1.8 v cmos clock source by connecting the source to either of the reference input pins (ref0_p or ref0_n, for example). connect t he unused input pin to gnd via a 0.1 n f capacitor. monitor clock input the mclk_x pins are the monitor clock input s and are intended to accept a stable frequency reference source. the mclk_x pins are configurable as either single - ended 3.3 v cmos or differen - tial. the monitor clock accepts a f ixed frequency of 0.008 mhz, 10 mhz, 19.44 mhz, 25 mhz, or 38.88 mhz. note that the monitor clock input frequency and receiver configuration depend on the scanned state of ppr6 (see the ppr6 monitor clock (mclk_x) i nput configuration section for details). a stable monitor clock frequency source supports the operation of the reference monitor (see the reference monitor section). because the reference monitor relies on the pre cision and stability of the monitor clock input signal, the user must ensure the frequency accuracy of the monitor clock source. reference switching the ad9574 provides for manual reference switch ing capability. although the on - board reference monitor provides the user with information regarding the status of the input references, the device does not provide for automatic reference switchover as a result of status changes. rather, the ref_sel pin p rovides the user with manual reference switchover control. a logic 0 on the ref_sel pin informs the internal reference switching logic to make ref0 the active reference, whereas a logic 1 makes ref 1 the active reference. the switch to a new active referenc e does not occur instantaneously with a corresponding change of state on the ref_sel pin. instead, the reference switching logic notes the request for a reference switch and waits for the opportune moment to make the physical switch. this functionality ens ures a minimal frequency disturbance on the output clocks associated with the integrated pll ( the out2 through out6 channels ). the reference switching logic provides information about which reference channel (ref0 or ref1) is the currently active reference via the ref_act output pin. the ref_act pin is logic 0 when ref0 is the active reference and logic 1 when ref1 is the active reference. furthermore, the reference switching logic indicates when the device is in the process of performing a reference switch over via the ref_sw pin (that is, ref_sw is logic 1 when a reference switch is in progress). the ref_sw pin assumes a logic 1 state when ref_sel changes states and returns to a logic 0 state when the device completes the reference switchover process. see t he reference switching section for additional information. changing the state of the ref_sel pin triggers the internal state machine to perform the reference switching process. be sure to confirm (via the ref_act pin) that the device has switched to the desired reference before a subsequent change of the ref_sel pin. changing the state of the ref_sel pin before the internal state machine completes the reference switching process may cause undesired results. becaus e the reference switching logic waits for an optimal switchover point rather than switching immediately , there is the rare possibility that either or both references happen to fail ( resulting in a loss of reference (lor) fault condition ) just after the use r requests a reference switchover (via the ref_sel pin) , but before the switching logic identifies the optimal switchover point. in such an instance, the lor condition associated with either reference causes the internal state machine to stall and the devi ce fails to switch references, thereby retaining the currently active reference. if the currently active reference fails, the device loses lock, thereby necessitating a device reset. if the requested reference fails, the device retains the currently active reference , but switches to the requested reference if it becomes available. note that as long as a reference remains in an lor condition, the state machine remains stalled. only a device reset makes the state machine disregard the initial request to switc h references. the ref_sel pin determines which reference is the active reference any time device power is cycled or the user asserts the reset pin. reference monitor an on - board refe rence frequency monitor provides the user with a means t o validate the frequency accuracy of the active reference channel (ref0 or ref1) in real time . the refmon pin enables or disables the reference monitoring function ( logic 1 or logic 0, respectively). be sure to apply a static and valid logic 0 or logic 1 l evel to the refmon pin. do not allow the refmon pin to float. do not toggle the refmon pin during device operation. when enabled, the reference monitor continuously tests the frequency of the active reference by comparing it to the frequency of the mclk _x signal . the result of this comparison rev. 0 | page 26 of 33
data sheet ad9574 appears on the ref_fhi and ref_flo pins per table 30 . the above or below frequency decision threshold of the monitor is 10 ppm, 25 ppm, 50 ppm , or 100 ppm per the scanned value of ppr5 (see the ppr5 reference monitor threshold section). following a power - up or reset , the reference monitor indicate s an indeterminate (see table 30 ) condition until enough time elapses to make a valid decision (see the monitor clock input to ref_fhi / ref_f lo time parameter in table 16 ). the monitoring process begins when the following two conditions are met: t he refmon pin is logic 1 and a valid signal is present at the mclk _x pin s. within the time specified by the monitor clock input to ref_fhi/ref_flo time parameter (per table 16 ) , the reference monitor indicate s the results on the r eference m onitor status pins , ref_fhi/ref_flo (per table 30) . the ref_fhi and ref_flo pins are open drain with internal pull - down resistors allowing wire - or e d operation . that is, both pins can be c onnected together to yield a single in tolera nce or out of tolerance indication. with a wire - or e d connection, however, it is not possible to discern whether the reference frequency is above or below the tolerance threshold. table 30. reference frequency monitor status ref_fhi ref_flo active reference status 0 0 frequency within tolerance threshold 0 1 frequency below tolerance threshold 1 0 frequency above tolerance threshold 1 1 indeterminate or fault condition in addition to its frequency monitoring function, t he reference monitor also check s for the presence of a clock signal at the ref0 _x , ref1 _x, and mclk _x inputs . the absence of a clock signal results in a n internal lor indication for that particular clock input . note that lor indication occurs when the input frequency is below approximately 1 mhz . the one exception is for f mclk = 8 khz , for which an lor indication occurs if f mclk is below approximately 6.1 khz . a n lor condition may cause the ref_fhi and ref_flo pins to ind icate an indeterminate state (a logic 1 on both the ref_fhi and ref_flo pins) . see the reference switching section for details regarding lor condi - tions that occur during a reference switching operation. pll the pl l consists of six functional elements. ? frequency prescaler ? pfd ? charge pump ? loop filter ? vco ? feedback divider the ad9574 automatically configures the six functional elements based on the prevailing ppr x settings. the prescaler is shown functionally as a programmable divider in figure 20 . it actually consists of a 2 frequency multiplier, a divide - by - 5 block , and multiplexers to yield the necessary frequency d ivide ratios per table 31. table 31 . pll frequency prescaler 2 5 frequency division active bypassed 1/2 (same as multiply by 2 ) bypassed bypassed 1 active active 5/2 bypassed active 5 table 32. ref_fhi and ref_flo status 1 ref mon mclk _x ref_ sel ref_ sw 2 ref0 _x ref1 _x ref_fx 3 0 not applicable 0 0 lor not applicable 11 0 not applicable 0 0 ok not applicable 00 0 not applicable 1 0 not applicable lor 11 0 not a pplicable 1 0 not applicable ok 00 0 not applicable not applicable 1 lor not applicable 11 0 not applicable not applicable 1 not applicable lor 11 0 not applicable not applicable 1 ok ok 00 1 lor not applicable not applicable not applicable not applica ble 11 1 ok 0 0 lor not applicable 11 1 ok 0 0 ok not applicable 00, 01 , or 10 1 ok 1 0 not applicable lor 11 1 ok 1 0 not applicable ok 00, 01 , or 10 1 ok not applicable 1 lor not applicable 11 1 ok not applicable 1 not applicable lor 11 1 ok not a pplicable 1 ok ok 00, 01 , or 10 1 ok means the signal is present. 2 for ref_sw = 1, lor means a transition to a lor condition while the device is in the process of a reference switchover. 3 ref_fx refers to the combined state of the ref_fhi and ref_flo pins per table 30. rev. 0 | page 27 of 33
ad9574 data sheet the pfd, charge pump , and loop filter work together to tune the vco output frequency according to the phase difference of the clock edges at the input to the pfd. the closed - loop configuration gradually causes the phase d ifference at the pfd input to settle near zero and the vco output frequency to settle to a value of n times the pfd input frequency (n is the feedback divider value). based on the ppr x pin settings, t he ad9574 automatically sel ects the value of n and the pre scaler value to yield one of three vco frequencies (2488 mhz, 2500 mhz, or 2560 mhz) per table 23. the loop filter consists of a partially integrated th ird - order r c network with an external network connected between the lf and ldo_byp pins . the external network consists of a 1 nf or 2 nf c apacitor or a series connected 2 nf capacitor, c, and 4.75 k? resistor , r (see table 33 ). the loop filter components, charge pump current, feedback divider , and vco gain define the bandwidth of the pll according to table 23. the de vice automatically adjusts the internal components per the ppr x settings to maintain an approximately constant loop bandwidth. table 33 . external loop filter components ppr 1 state external components 0 c = 1 nf 1 c = 2 nf 2 c = 1 nf 3 c = 2 nf 4 c = 1 nf 5 c = 2 nf 6 c = 2 nf in series with r = 4.75 k 7 c = 2 nf in series with r = 4.75 k figure 22 is a diagram of the loop filter portion of the pll. f igure 22 . pll loop filter detail the ad9574 also provides a digital lock detect output signal at the ld pin, which indicates (active high) when the device considers the pfd input phase differential to have stabilized near zero . the out2 through out6 ch annels are static ( outputs do not toggle) while the pll is unlocked ( that is, while the ld pin is logic 0). output drivers the o utput c hannels o f the ad9574 offer the f lexibility o f a variety of d rive formats, including hstl, hcsl, lvds, and cmos. each channel offers a subset of these formats (see table 34). table 34. output drive fo rmats output channel format hstl hcsl lvds cmos 3.3 v 1.8 v 0 yes no no yes no 1 yes no no yes no 2 yes no no no no 3 yes no no no no 4 yes yes yes no no 5 yes yes yes no no 6 no no yes yes yes output clocks the seven output clock channels (out0 through out6) provide two different frequency translation functions. out0 and out1 offer a replica of the reference frequency ( with a frequency doubling option for out0 ), whereas out2 through out6 offer rational frequency translations by means of an integrated integer - n pll. table 35 shows a summary of the available frequencies for each output channel (in units of mhz) . the indicated reference to output frequency translations depend s on the results of a ppr x scan (see the pprx pins section for details). table 35 . output frequencies f ref output (mhz) 0 1 2 3 4 5 6 25 25 25 156.25 156.25 100 100 33.33 50 125 125 66.6 7 312. 5 312.5 133.3 80 80 160 160 19.44 19.44 19.44 155.52 155.52 38.88 38.88 n/a 1 77. 76 77.76 1 n/a means not applicable. charge pump integr a ted loo p fi lter vco external components ldo_byp lf 07501-017 rev. 0 | page 28 of 33
data sheet ad9574 applications informa tion dual - oscillator reference input application figure 23 depicts a typical application diagram using two crystal oscillators (xos) as th e reference inputs . a stable oscillator source supplies the mclk _x input s and serves as the timing reference for the on - board reference monitoring function . a field - programmable gate array (f pga ) handles the control interface for monitoring the status of t he references and the pll (lock detector) and for switching between references as required. the fpga also controls the on/off state of the reference oscillators, which provides for shutting down a faulty reference or for keeping a redundant reference turned off until needed . the general configuration of the ad9574 is set via a group of resis tors that establish the desired ppr x states . although figure 23 shows xos with differential outputs, single - ended xos can be substituted by connecting the xo output to the refx_p pin and a 0.1 nf capacitor from the refx_n pin to gnd. figure 23 . dual - oscillator reference input application diagram rx rx reference monitor ad9574 pfd/ cp lf vco ppr control 1/2 1/2 ref0_p ref0_n ref1_p ref1_n mclk_p mclk_n ref_act ref_sw ref_fhi ref_flo ref_sel refmon out0_n out0_p out1_n out1_p out2_n out2_p out3_n out3_p out4_n out4_p out5_n out5_p out6_n out6_p ld lf ldo_byp 1nf 470nf 07501-018 47 41 7 27 26 24 19 1 2 6 5 45 46 48 25 35 34 44 43 11 12 38 37 39 40 29 28 32 33 22 21 10 9 14 15 16 dividers stable reference fpga xo xo on/off control ppr0 programming resistors 3.3v ppr1 ppr2 ppr3 ppr4 ppr5 ppr6 rev. 0 | page 29 of 33
ad9574 data sheet simple, single - oscillator reference input application figure 26 depicts a simple application using a single crystal oscillator as the reference input with minimal reference monitoring functionality. the wire - ored ref_fhi and ref_flo connection in conjunction with ref_mon tied to gnd (ref_mon = 0; see table 32 ) yields a lor func tion indicating only that re f0 is present (or not); that is, there is no specific indication of high or low frequency status. the lor and ld signals can notify a controller (not shown) of a reference failure or an unlocked pll condition. the general configuration of the ad9574 is set via a group of resistors that establish the desired pprx states. although figure 26 shows an xo with differential outputs, a single - ended xo can be subst i - tuted by connecting the xo output to the ref0_p pin and a 0.1 n f capacitor from the ref0_n pin to gnd. interfacing to cmos clock outputs apply the following general guidelines when using the single - ended 1.8 v or 3.3 v cmos clock output drivers. design p oint - to - point nets such that a driver has only one receiver on the net, if possible. this allows simple termination schemes and minimizes ringing due to possible mismatched impedances on the net. series termination at the source is generally required to pr ovide transmission line matching and/or to reduce current transients at the driver. the value of the series termination depends on the board design and timing requirements (typically 10 ? to 100 ?). cmos outputs are limited in terms of the capacitive load or trace length that they can drive. typically, trace lengths less than 6 inches are recommended to preserve signal rise/fall times and signal integrity. figure 24 . series termination of cmos output termination at the far end of the printed circuit board ( pcb ) trace is a second option. the cmos outputs of the ad9574 do not supply enough curren t to provide a full voltage swing with a low impedance resistive, far end ter mination, as shown in figure 25 . ensure that the impedance of the far end termination network match es the pcb trace impedance and provide s the desired switching point. the reduced signal swing may still meet rec eiver input requirements in some applications. this can be useful when driving long trace lengths on less critical nets. figure 25 . cmos output with far end termination 10? microstrip gnd 5pf 60.4? 1.0 inch cmos 07499-015 50? 10? 3.3v cmos 5pf 100? 100? 07501-021 rev. 0 | page 30 of 33
data sheet ad9574 figure 26 . single - oscillator r eference input application diagram interfacing to lvds and hstl clock outputs lvds and hstl both employ a differ ential output driver . the recommended termination circuit for lvds and hstl driver s appears in figur e 27. figure 27 . lvds or hstl output termination see the an - 586 application note on the analog devices website at www.analog.com for more information about lvds. interfacing to hcsl clock outputs hcsl uses a differential open - drain architecture. the open - drain architecture necessitates the use of an external termination resistor. figure 28 shows the typical method for interfacing to hcsl drivers . figure 28 . hcsl output termination in some cases, the fast switching capability of hcsl drivers results in overshoot and ringing. the alternative hcsl interface shown i n figure 29 can mitigate this problem via a small series resistor, typically in the 10 ? to 30 ? range. figure 29 . alternate hcsl output termination rx rx reference monitor ad9574 pfd/ cp lf vco ppr control 1/2 1/2 ref0_p ref0_n ref1_p ref1_n mclk_p mclk_n ref_act ref_sw ref_fhi ref_flo ref_sel refmon out0_n out0_p out1_n out1_p out2_n out2_p out3_n out3_p out4_n out4_p out5_n out5_p out6_n out6_p ppr0 ld lf programming resistors 3.3v ldo_byp 1nf 470nf 07501-019 lor ld xo 47 41 7 27 26 24 19 1 2 6 5 45 46 48 25 35 34 44 43 11 12 38 37 39 40 29 28 32 33 22 21 10 9 14 15 16 dividers ppr1 ppr2 ppr3 ppr4 ppr5 ppr6 hstl/lvds driver 100 ? receiver independent uncoupled 50 ? transmission lines 07501-022 hcsl 50 ? 50 ? receiver independent uncoupled 50 ? transmission lines 07501-023 hcsl 50 ? 50 ? independent uncoupled 50 ? transmission lines receiver 10 ? to 30 ? 10 ? to 30 ? 07501-024 rev. 0 | page 31 of 33
ad9574 data sheet p ower supply the ad9574 requires a power supply of 3.3 v 10% . the specifications section give s the performance expected from the ad9574 with the power supply voltage within this range. the absolute maximum range of ?0.3 v to +3.6 v, with respect to gnd, must never be exceeded on the vdd _x pin s. follow g ood engineering practice in the layout of power supply traces and the ground plane of the pcb. bypass t he power supply on the pcb with adequate c apacitance (>10 f). bypass t he ad9574 with adequate capacitors (0.1 f) at all power pins as close as possible to th e device . the layout of the ad9574 evaluation board is a good example of h ow to route power supply traces and where to place bypass capacitors . the ex posed metal pad on the ad9574 package is an electrical connection, as well as a thermal enhancement. for the device to f unction properly, the pad must be properly attached to ground (gnd). the pcb acts as a heat sink for the ad9574 ; therefore, this gnd connection provide s a good thermal path to a larger heat dissip ation area, suc h as a ground plane on the pcb. power and grounding considerations and power supply rejecti on many applications seek high speed and performance under less than ideal operating conditions. in these application circuits, the implementation an d construction of the pcb is as important as the circuit design. proper rf techniques must be used for device selection, placement, and routing, as well as for power supply bypassing and grounding to ensure optimum performance. rev. 0 | page 32 of 33
data sheet ad9574 rev. 0 | page 33 of 33 outline dimensions figure 30. 48-lead lead frame chip scale package [lfcsp_wq] 7 mm 7 mm body, very thin quad (cp-48-5) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD9574BCPZ ?40c to +85c 48-lead lead frame chip scale package [lfcsp_wq] cp-48-5 AD9574BCPZ-reel7 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_wq] cp-48-5 ad9574/pcbz evaluation board 1 z = rohs compliant part. for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. compliant to jedec standards mo-220-wkkd. 1 0.50 bsc bottom view top view pin 1 indicator 7.00 bsc sq 48 13 24 25 36 37 12 exposed pad p i n 1 i n d i c a t o r 4.25 4.10 sq 3.95 0.45 0.40 0.35 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 min 0.20 ref coplanarity 0.08 0.30 0.23 0.18 08-16-2010-b ?2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07501-0-10/14(0)

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